1. Field
This patent document relates to a semiconductor design technology, and more particularly, to a test method of a memory device having an on-chip error correction code (ECC) scheme.
2. Description of the Related Art
As memory devices shrink in size, fail data randomly occurs which increases soft errors. Therefore, in order to address such a concern, an on-chip ECC scheme has been recently employed by mounting an ECC function in a memory device. That is, a memory device may perform a repair operation of replacing repair target memory cells with redundancy memory cells or may correct an error thereof based on the on-chip ECC scheme.
To implement the on-chip ECC scheme, a parity bit for ECC may be allocated and stored into a specific space. In particular, a memory device employing the on-chip ECC scheme may allocate and store a parity bit for ECC into memory cells included in a memory array region. Hereafter, the memory cells for storing the parity bit for ECC will be referred to as ‘ECC memory cells’.
In general, after all fabrication processes are completed, a test is performed on memory devices to measure various characteristics of the memory devices formed on a semiconductor substrate. Such a test can detect a defect in processes such as the fabrication process and assembly process of the semiconductor substrate, thereby increasing the throughput of the memory devices.
In particular, a wafer test of testing a memory device at the wafer level includes a parallel bit test (PBT) for reducing the test time. The PBT may include writing specific test data to all memory cells, and determining a pass/fail by comparing the specific test data with the written test data outputted through a global data line from the memory cells.
However, in a memory device employing the on-chip ECC scheme, parity bits for correcting errors of normal cells are written to ECC memory cells. Thus, the memory device cannot be tested through the PBT that writes the same test data to normal cells and ECC memory cells, reads the written test data, and compares the read test data with the original test data.
Therefore, research needs to be conducted on a method capable of efficiently performing a parallel test on a normal cell region for storing normal cells and a parity cell region for storing ECC memory cells.